1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a semiconductor device in which polysilicon is used to form source and drain regions in an initial process step so as to reduce resistance of bit lines and minimize a junction capacitance and thus improve its reliability, and a method for fabricating the same.
2. Discussion of the Related Art Due to buried N.sup.+ layers(hereinafter referred to as BN.sup.+ layer), which is used in flash EEPROM cells and mask ROM cells, it is possible to make virtual ground, and the number of contact holes is diminished to reduce sizes of chips. Source and drain regions are commonly formed in a final process step in a case a semiconductor device is fabricated using BN.sup.+ layers.
A conventional method for fabricating a semiconductor device will be described with reference to FIGS. 1A to 1C which are cross-sectional views showing process steps of a method for fabricating a semiconductor device.
First, a photoresist film is coated on a semiconductor substrate 11 or a p well as shown in FIG. 1A. In this case, instead of a photoresist film 13 alone being coated, an insulating layer is first deposited on a semicondutor substrate 11 and then a photoresist film 13 is coated on the insulating layer.
Next, as shown in FIG. 1B, the photoresist film 13 over placements of BN.sup.+ layers is patterned by exposure and development processes. N.sup.+ heavily doped impurity ions are implanted into the semiconductor substrate 11 by using the photoresist pattern 13 as a mask.
Subsequently, the remaining photoresist film 13 is removed as shown in FIG. 1C. Then an annealing process is performed to grow a gate oxide layer 15 on the semiconductor substrate 11 and simultaneously form BN.sup.+ layers 17. At this time, the BN.sup.+ layers 17 function as source and drain regions. The gate oxide layer 15 is thicker on the BN.sup.+ layers than on the semiconductor substrate 11 because the BN.sup.+ layers have a high concentration of impurity ions.
According to a conventional method for fabricating a semiconductor device, source and drain regions are formed in an initial process step and gate electrodes are formed right over the source and drain regions so that it can be possible to make virtual ground and the number of contact holes in a cell is minimized to reduce the area of a chip.
However, it has following problems. There is a reduced a voltage applied to bitlines in contact with BN.sup.+ layers due to a resistance of the BN.sup.+ layers. Moreover, since a junction area of the BN.sup.+ layers and a semiconductor substrate increases and thus a junction capacitance on the junction area increases, operational speed of the semiconductor device is lowered.